AMD Next Generation Processor Technology Slides

[brentpresley]

Thank you for getting emotional about silicone. I'm sure behavioral researchers will have a good time with this.

ROTFLMAO - this made my night.

Silicone huh?

FYI, the stuff used for the old BREAST implants is not the stuff used for wafers.

It is called SILICON (no E at the end).

I don't need you to give me the last word.

I didn't come to this forum to post or to target you. I come here to read up on hardware recommendations, mobo recommendations, interesting things about case mods...etc

It is very insulting to me (and I'm sure others who are working in this field) when I see people mis-quote information from the web and then try to pass off BS as facts. This is the only reason I'm posting on this thread.

I have used AMD chips from K6-2 to now Athlon64 X2. I am extremely happy with my choice of AMD chips for the past 10 years because I know I was able to pick a chip for its merit regardless of brand (price/performance). I think people should be able pick products based on price/performance instead of brand.

What I think is useless is speculating about performance of future products (this is the reason why everyone hates a paper launch from ATi or Nvidia). What is more useless is arguing about AMD yields or their manufacturing management system to which no one knows anything about unless he/she works at AMD. What is the most useless is people who quote these useless information for the sake of winning a debate.

I think it is really sad that people like you are dumbing down this forum. It is even more sad that you're on the AMD side. People like you were on the Intel side 10 years ago.

So if you continue to post BS as facts, I will continue to call you out. I do not want people who come here to read up on hardware informations to be misinformed.

A gentleman and a scholar. Well thought post.

 

[brentpresley]

What's even more useless is those people that argue about other people and there attempts to shed light on the current situation. Then try to pass it off as some sort of holy plight against evil...

Get off my nuts dude. It's fun to swing but there comes a point when the ride is over, and it's time to get off.

As usual, you have no LOGICAL or FACTUAL retort, so you spout crap.

TROLL ALERT.

 

[(cf)Eclipse]

As usual, you have no LOGICAL or FACTUAL retort, so you spout crap.

TROLL ALERT.

you baited him. all of you guys need to cut out the personal comments on others. it's sickening me. to top it off, you quote lolento's post as well thought out and scholorly, while he has the same amount of proof as what duby is saying, who is a troll with no logical or factual retort. that in itself is amusing as it is not a logical or factual retort, but your own opinion.

90nm process was hovering at 70% at the time I left my previous work last year in September.

Continuous process improvement never stops. However, it is from my experience that once about 70% yield is reached, further improvement is difficult. But the work for improvement continues.

When cache and cores are disable to improve yield. That technique is called binning in wafer test. I'm saying even with large number of binning, the yield is still difficult to reach 70%.

I don't know exactly what the yield levels are for AMD, Intel, TSMC, SMIC, UMC, or IBM. But I can tell you that the engineers at these companies move around quite often. What I know from one company basically translate to the others.

i guess i'll just have to take your word for it, but this is the first time i've heard about this 70% yield limit.. if you could support this information in any way, i would be appreciative

 

[duby229]

I didn't come to this forum to post or to target you. I come here to read up on hardware recommendations, mobo recommendations, interesting things about case mods...etc

As do I, Nothing wrong with contributing to the forum. After all that is what it is here for.

It is very insulting to me (and I'm sure others who are working in this field) when I see people mis-quote information from the web and then try to pass off BS as facts. This is the only reason I'm posting on this thread.

Wrong I clearly stated to you and others that I was speculating precisely becouse FACTS are not known,.. I did quote OTHER facts in support of my speculation however, which is much more then you have done.

I have used AMD chips from K6-2 to now Athlon64 X2. I am extremely happy with my choice of AMD chips for the past 10 years because I know I was able to pick a chip for its merit regardless of brand (price/performance). I think people should be able pick products based on price/performance instead of brand.

What I think is useless is speculating about performance of future products (this is the reason why everyone hates a paper launch from ATi or Nvidia). What is more useless is arguing about AMD yields or their manufacturing management system to which no one knows anything about unless he/she works at AMD. What is the most useless is people who quote these useless information for the sake of winning a debate.

I've already said my peace on this beauty of whatever it is supposed to be...

I think it is really sad that people like you are dumbing down this forum. It is even more sad that you're on the AMD side. People like you were on the Intel side 10 years ago.

Ohh Ok, so know you know all about me... K... Love you too honey

So if you continue to post BS as facts, I will continue to call you out. I do not want people who come here to read up on hardware informations to be misinformed.

Again since you like like to be so close to my nuts, I think I'll get out a picnic, and some sandwhiches, and some vasaline...

For your information, you're right about the partial dice not being counted on the yield. However, even full dice along the perimeter has a high defect rate, and they are counted in the yield. I don't think AMD can improve the yield of these full edge dice due to the fact that it is not the process that is causing the defect; the coplanarity of the wafer at the edge is causing most of these defects.

Of course, but for those that have bad cache, it disabled and sold as a lower end part, for those that have a bad core, it gets disabled and sold as a lower end part. For those that dont meet thermal requirements, it gets sold as a lower end part... I think you'll find that most still function to a usable extent in some capacity.

 

[Lolento]

Of course, but for those that have bad cache, it disabled and sold as a lower end part, for those that have a bad core, it gets disabled and sold as a lower end part. For those that dont meet thermal requirements, it gets sold as a lower end part... I think you'll find that most still function to a usable extent in some capacity.

Sorry, have to call BS on that. As I said, edge die defects are not point defects, they are usually caused by the coplanarity of the wafer at the edge (or lack thereof). These are usually bin "x". I'm not a test guy, bin X are scraps.

 

[(cf)Eclipse]

Sorry, have to call BS on that.

on the fact that amd sells chips with 1/2 or more of the cache disabled or one whole core disabled for the dual cores with a defect in the die?

i hate to say it, but you obviously never worked for AMD's fabs.

the sempron i have? same stepping as a 512kb cache orleans. it inidicates that there are 512kb cache on die, but the chip only uses 256kb of it. 1/2 cache disabled for the hell of it? i think not, it was disabled, presumeably due to a defect. why throw out what can be sold as a lower chip?
there are also two s939 chips, the E4 512kb chips and E6 1mb chips, both single core, but when the lid is popped, the die size is the same as the manchester or toledo that it used to be.

search for "E6 san diego amd", you'll see that everyone else agrees with me. it's NOT BS, amd does this to improve effective yields, as i have been saying all along.

 

[duby229]

Sorry, have to call BS on that. As I said, edge die defects are not point defects, they are usually caused by the coplanarity of the wafer at the edge (or lack thereof). These are usually bin "x". I'm not a test guy, bin X are scraps.

Whatever dude, At least I provided verifiable evidence for my claim. I may be wrong in the end, but right now nobody has shown anything to the contrary.

Like I said, I've already shown what AMD is capable of making, and what they are selling... Almost everything they can make, they are selling... It's called logic, and imperical evidence.

 

[(cf)Eclipse]

imperical evidence.

which the guys arguing against us seem to have surprisingly little of, eh?

 

[Lolento]

on the fact that amd sells chips with 1/2 or more of the cache disabled or one whole core disabled for the dual cores with a defect in the die?

i hate to say it, but you obviously never worked for AMD's fabs.

the sempron i have? same stepping as a 512kb cache orleans. it inidicates that there are 512kb cache on die, but the chip only uses 256kb of it. 1/2 cache disabled for the hell of it? i think not, it was disabled, presumeably due to a defect. why throw out what can be sold as a lower chip?
there are also two s939 chips, the E4 512kb chips and E6 1mb chips, both single core, but when the lid is popped, the die size is the same as the manchester or toledo that it used to be.

search for "E6 san diego amd", you'll see that everyone else agrees with me. it's NOT BS, amd does this to improve effective yields, as i have been saying all along.

You don't understand what I'm saying.

Binning works on localized defects, in which case disabling 1/2 cache would work.

I'm saying you usually can't bin the edge dice that are deemed defective because their foundation is bad.

If you appreciate the concept of photo lithography, it is a process of building a 3D structure by manipulating only the z-axis. Or a "build up" process. In case of the edge of the wafer, the surface uniformity is hard to control there and thus dice in that area will have high defect rate. These defects cannot be sourced to a single point and thus disabling certain features on the chip would not make it functional.

FYI, AMD is not the only company that bins their chip.....hahaha

 

[Lolento]

Whatever dude, At least I provided verifiable evidence for my claim. I may be wrong in the end, but right now nobody has shown anything to the contrary.

Like I said, I've already shown what AMD is capable of making, and what they are selling... Almost everything they can make, they are selling... It's called logic, and imperical evidence.

I'm saying that you're twisting the sources of your claim and making your interpretation of it. And I'm telling you that this is insulting.

By the way, it is EMPIRICAL not imperical. Empirical means supported by experiment or science. All of the things that I posted here should be supported by empirical data. I'm sure people who have attended at least a few college course in this area should know what I'm saying.

 

[(cf)Eclipse]

whereas you are just saying stuff without having any links or proof to what you're saying. in my eyes, it's better to read something, twist the words for your own interpretation and provide linkage for others to draw their own conclusion than just randomly state something. who knows, i could have randomly said that i'm a fab engineer at tsmc and that their 90nm parts are at 57% yield!

I'm saying you usually can't bin the edge dice that are deemed defective because their foundation is bad.

you're either saying:

1. the chips on the edge are not complete dies, thus are defective.
2. the chips near the edge have a very high defect rate and very rarely work.

to one, obviously.
two, if this is the case, why are we moving to larger wafer sizes. from my understanding, the technology has gotten to the point where yield is much more uniform across the wafer than it was before, to the point where it make economic sense to increase wafer area 125% (200mm to 300mm diameter) because yields at the edge are actually pretty good.

 

[brentpresley]

whereas you are just saying stuff without having any links or proof to what you're saying. in my eyes, it's better to read something, twist the words for your own interpretation and provide linkage for others to draw their own conclusion than just randomly state something. who knows, i could have randomly said that i'm a fab engineer at tsmc and that their 90nm parts are at 57% yield!


you're either saying:

1. the chips on the edge are not complete dies, thus are defective.
2. the chips near the edge have a very high defect rate and very rarely work.

to one, obviously.
two, if this is the case, why are we moving to larger wafer sizes. from my understanding, the technology has gotten to the point where yield is much more uniform across the wafer than it was before, to the point where it make economic sense to increase wafer area 125% (200mm to 300mm diameter) because yields at the edge are actually pretty good.

Simple math. As you increase the radius of a circle, the ratio of the circumfrence to the area becomes smaller and smaller (i.e. the rate of increase of the number of chips overall, to the chips at the edge is getting bigger).

circumf = pi x radius x 2
area = pi x radius^2

Assuming the bad chips at the edge are only those chips within say 1cm of the edge (arbitrary value, but any value you pick holds up), increasing the size of the wafer allows you to broaden the "sweet spot", so to speak, that you can get "good" yields from.

 

[duby229]

I'm saying that you're twisting the sources of your claim and making your interpretation of it. And I'm telling you that this is insulting.

By the way, it is EMPIRICAL not imperical. Empirical means supported by experiment or science. All of the things that I posted here should be supported by empirical data. I'm sure people who have attended at least a few college course in this area should know what I'm saying.

Well, I'm an american.. What can I say. I didnt pay attention english class 15 years ago.. Sorry.

Empirical evidence is a collection of analysis, which points to a conclusion... It is evidence of a certain outcome based on experience, or experiments

Depending upon experience or observation alone, without
due regard to science and theory; -- said especially of
medical practice, remedies, etc.; wanting in science and
deep insight; as, empiric skill, remedies.
[1913 Webster]

Anyway. It is simply symantics... Who cares the point is that AMD is selling pretty close to what the fabs theoretical maximum is... Which if you think about is an indicator of yeild... It doesnt tell us what the yeild is, but it does tell us that the yeild is pretty damn good.

Sorry if this is too much for you.

 

[(cf)Eclipse]

Simple math. As you increase the radius of a circle, the ratio of the circumfrence to the area becomes smaller and smaller (i.e. the rate of increase of the number of chips overall, to the chips at the edge is getting bigger).

circumf = pi x radius x 2
area = pi x radius^2

Assuming the bad chips at the edge are only those chips within say 1cm of the edge (arbitrary value, but any value you pick holds up), increasing the size of the wafer allows you to broaden the "sweet spot", so to speak.

as lolento said to me, i don't think you understood my post. re-read it and rethink what i said.
and obviously i know the circumfrence and area equations, if i was able to figure that a 50% increase in diameter = 125% increase in area..

 

[Lolento]

Well, I'm an american.. What can I say. I didnt pay attention english class 15 years ago.. Sorry.

Empirical evidence is a collection of analysis, which points to a conclusion... It is evidence of a certain outcome based on experience, or experiments



Anyway. It is simply symantics... Who cares the point is that AMD is selling pretty close to what the fabs theoretical maximum is... Which if you think about is an indicator of yeild... It doesnt tell us what the yeild is, but it does tell us that the yeild is pretty damn good.

Sorry if this is too much for you.

That's fine.

I just hope that you don't post your interpretation of anything as facts. I can guarantee that AMD is not close to 100% (or even 80%) yield at 90nm process because no one else is. Other than the few principal scientists, the engineer base of every one of these company came from the same pool. I don't think the technical know-how of AMD is that much better than the other companies. Especially considering their progress with 65nm.

 

[duby229]

Logic and empirical evidence doesnt support your conclusion. But I guess that is how we will have to leave it.

I'm done debating this. We will never know for sure so I'll let you have the last word.

I'm out.

 

[Lolento]

as lolento said to me, i don't think you understood my post. re-read it and rethink what i said.
and obviously i know the circumfrence and area equations, if i was able to figure that a 50% increase in diameter = 125% increase in area..

actually, i don't think you understand math either.

when you increase the wafer size from 200mm (8 inch) to 300mm (12 inch), the edge to area ratio is decreased by 40%.

just use the formulas that Brentpresley showed you.....

 

[(cf)Eclipse]

I'm done debating this

double shift for me



lolento, i was talking total surface area. the % of chips on the edge is a bit more complicated due to variations in chip size and geometry.. you also never made any comment on the "near edge" yields.. which is what i thought you were talking about after rereading your post for the 3rd time

as a side note, i'm slightly insulted. i guess i haven't made it out of middle school yet so i don't know basic geometry

 

[enumae]

...the point is that AMD is selling pretty close to what the fabs theoretical maximum is... Which if you think about is an indicator of yeild... It doesnt tell us what the yeild is, but it does tell us that the yeild is pretty damn good.

I am not trying to beat a dead horse, but could you link the two parts of your claims...

1. How many wafer starts per month.

2. How many processors sold per quarter.

Thanks.

 

[(cf)Eclipse]

wafer starts per month = ~30,000
http://www.theinquirer.net/default.aspx?article=31095

no idea how many chips are sold each month.

 

[Lolento]

double shift for me



lolento, i was talking total surface area. the % of chips on the edge is a bit more complicated due to variations in chip size and geometry.. you also never made any comment on the "near edge" yields.. which is what i thought you were talking about after rereading your post for the 3rd time

as a side note, i'm slightly insulted. i guess i haven't made it out of middle school yet so i don't know basic geometry

You don't need to calculate the geometry exactly.

Ratio stays pretty much the same given the same die size and the shift is from 200mm to 300mm wafer.

Just put a graphing paper on a circle. The number of units you can fit on the perimeter divided by the number of units you can fit within the area (or ratio of perimeter over area) remain the same regardless whether you use a 1mm^2 die or a 20mm^2 die. Try it before you write it off.

Then see how this ratio decreases by increasing the area of the circle. Try it before you write it off.

Don't be ignorant.

 

[(cf)Eclipse]

You don't need to calculate the geometry exactly.

Ratio stays pretty much the same given the same die size and the shift is from 200mm to 300mm wafer.

Just put a graphing paper on a circle. The number of units you can fit on the perimeter divided by the number of units you can fit within the area (or ratio of perimeter over area) remain the same regardless whether you use a 1mm^2 die or a 20mm^2 die. Try it before you write it off.

Then see how this ratio decreases by increasing the area of the circle. Try it before you write it off.

Don't be ignorant.

yes, i know, the bigger the die, the better the area:circumfrence ratio... did i ever say otherwise?

but if you're calculating yields without the ones on the edge counted, what difference does it make? stop going off on tangents and reply to the real content of my post... the one that's being ignorant here is not me BANANAPHONE ATE MY KITTY! and this will show up when you quote me or highlight me. why is it that everyone always assumes that i am ignorant, clueless, or lump me with the "blind amd fan" stereotype. i thought i've provided enough indication by now that i'm not, and i will not give up until you've replied to the following comments:
first point - where i mention that you say that duby's "facts" are "wrong" based on what your "facts" are, without actually providing any proof for anything

second point - you keep ignoring what duby and i say about how amd rebins things by disabling varying amounts of cache. to be honest, i don't think this is something that intel does. if you can prove me otherwise, i'd be delighted to see evidence of this

third point - though it sounds like you're trying to say that the edge dies are included in the final yield %, you haven't given a clear answer one way or another. stop beating around the bush and tell me which of my interpretations of what you said is correct...

 

[duby229]

edited becouse I figured the answer on my own... Sorry.

 

[savantu]

I gotta call BS...

Anything less then 80% yeild is unmaintainable. If a company is consistantly getting less then 80% yeild, then it is time to evalute the situation....

Right now on AMD's 90nm SOI process the FAB is pushing out about 30M wafers a month... It was designed for 20M.... That means that AMD is at 150% capacity with damn near 100% yeilds....

Savantu of all people you should know anything less then 80% yeilds loses money.

Dubby stop talking out of your bottom.Reality isn't what you ( or whoever else ) want it to be .Find some engineers , talk to them , read FAB sites and you'll get a clue on yields.

If you want to have a rough clue on AMD's yeilds see how many CPUs they can produce in theory ( the mix is 75-25% SC-DC , die sizes known ) and actually compare what they ship ( there was a hkepc.com link on that ).

 

[savantu]

Thank you for getting emotional about silicone. I'm sure behavioral researchers will have a good time with this.

And maybe you'll get a clue that silicone is a polymer associated mostly with boobs right now.

Silicon ( lat. silicium ) is the chemical element we're so freaked about.

 

[savantu]

but i do have to wonder... you're arguing against him, also without any hard facts. why must you expect facts from him if you won't use them too? seems a touch skewed to me. best we can do when it comes to yields is either:
1. guess
2. work for amd and be under nda.

I posted a link from Fabtech where it say black on white that Chartred has yields as good as AMD even better on some batches , but even so they hover around 50%.

What has duby&co showed except idiotic preconceived ideas and ignorance ?

 

[savantu]

Logic and empirical evidence doesnt support your conclusion. But I guess that is how we will have to leave it.

I'm done debating this. We will never know for sure so I'll let you have the last word.

I'm out.

You lack both big time.You're in a world of your own , get a clue man , you badly need it.

You have no wish to learn or bring something valuable to this forum , in other words you are completly useless.If I need to laugh at a who-can-spew-the-biggest-crap I can go to your mentor , sharikou's blog ( wondering if you're not the same twit ).But don't bring that level of "knowledge" here , we can do very fine without it.

What is saddening is that apparently reasonable and intelligent people side with you , but at 15 wearing horse glasses is understandable.

 

[(cf)Eclipse]

I posted a link from Fabtech where it say black on white that Chartred has yields as good as AMD even better on some batches , but even so they hover around 50%.

What has duby&co showed except idiotic preconceived ideas and ignorance ?

you mean this post?
http://www.hardforum.com/showpost.php?p=1029872977&postcount=124

AMD's first foundry partner, Chartered Semiconductor has already been able to produce fully working die with yields equal to or even better than those achieved at AMD, according to a March 15th report from Bear Stearns.The reports authors said that yields were at 50 percent at Chartered's Fab7 but sometimes even better than those achieved within AMD's own fab!

so if it's at 50%, but sometimes better than what AMD gets, common sense dictates that AMD is getting better than 50% and sometimes Chartered gets bursts of good yields, no? The first line is is obviously FUD meant to make investors happy as it contradicts the second line. still no answer on what AMD is getting, but we know it's over 50%

btw, you guys know that obi qwiet just had a typo, i love how everyone had to jump on him for adding an e... something i see a lot of people do.
you didn't care when visaris said it - http://www.hardforum.com/showpost.php?p=1029838484&postcount=39
stop being so damn picky and focus on the arguement at hand...

speaking of which, this is so offtopic, it's rediculous. what is the point you're trying to prove anyway, other than just being disagreeable because of our "idiotic preconceived ideas and ignorance"?
grew a pair and learn how to prove us wrong without the childish comments that all 4 of your last posts are, along with the vague retorts on our general intelligence level. until we see that..... BATTLE TO THE DEATH!

 

[duby229]

Dubby stop talking out of your bottom.Reality isn't what you ( or whoever else ) want it to be .Find some engineers , talk to them , read FAB sites and you'll get a clue on yields.

If you want to have a rough clue on AMD's yeilds see how many CPUs they can produce in theory ( the mix is 75-25% SC-DC , die sizes known ) and actually compare what they ship ( there was a hkepc.com link on that ).

I know what ratio of chips AMD is making now... No need to be cocky. I If you'd like I can even post some evidence to back it up.

Besides I've already done just as you suggested.... Maybe you should actually go back and read what I posted in this thread.

 

[duby229]

And maybe you'll get a clue that silicone is a polymer associated mostly with boobs right now.

Silicon ( lat. silicium ) is the chemical element we're so freaked about.

Stop being a !!!!!!. Poeple misspell things... It's alright. As a wise stupid man once said... "Shit happens"

 

[duby229]

I posted a link from Fabtech where it say black on white that Chartred has yields as good as AMD even better on some batches , but even so they hover around 50%.

What has duby&co showed except idiotic preconceived ideas and ignorance ?

Your link to the fabtech article only says that Chartered gets worse yeilds then AMD, with an occasional boost here and there..

 

[duby229]

You lack both big time.You're in a world of your own , get a clue man , you badly need it.

You have no wish to learn or bring something valuable to this forum , in other words you are completly useless.If I need to laugh at a who-can-spew-the-biggest-crap I can go to your mentor , sharikou's blog ( wondering if you're not the same twit ).But don't bring that level of "knowledge" here , we can do very fine without it.

What is saddening is that apparently reasonable and intelligent people side with you , but at 15 wearing horse glasses is understandable.

You can attack me... But I can clearly see your nuts

Ok, seriously First of all let me just say you can stop with the !!!!!!ism... Go back to your hole and get a clue... Dont let the door hit you on the out.

 

[Lolento]

yes, i know, the bigger the die, the better the area:circumfrence ratio... did i ever say otherwise?



[third point - though it sounds like you're trying to say that the edge dies are included in the final yield %, you haven't given a clear answer one way or another. stop beating around the bush and tell me which of my interpretations of what you said is correct...

Full edge dice are calculated in the yield. This is not the first time I had express this.
The actual portion of the yield that the edge dice account for depends on die size. As you said the bigger the die, the bigger portion of the yield it will take up.

 

[Lolento]

Your link to the fabtech article only says that Chartered gets worse yeilds then AMD, with an occasional boost here and there..

Yea, it is funny what business sense AMD has.... they can achieve 100% yield internally but their partner is only doing 50%.

If I was AMD, I would send a few engineers out to singapore to bring CSM's yield up to 100%....hahaha

 

[Lolento]

yes, i know, the bigger the die, the better the area:circumfrence ratio... did i ever say otherwise?

Actually, the bigger the WAFER, the better the area:circumference ratio. But as the die gets bigger, this ratio gets worse.

 

[Lolento]

second point - you keep ignoring what duby and i say about how amd rebins things by disabling varying amounts of cache. to be honest, i don't think this is something that intel does. if you can prove me otherwise, i'd be delighted to see evidence of this

I don't know what Intel does or what AMD does. But disabling features on a die that has localized defect is not a new method that AMD developed. I don't think AMD should get credit for this.

 

[drizzt81]

What I think is useless is speculating about performance of future products (this is the reason why everyone hates a paper launch from ATi or Nvidia). What is more useless is arguing about AMD yields or their manufacturing management system to which no one knows anything about unless he/she works at AMD. What is the most useless is people who quote these useless information for the sake of winning a debate.

I agree.

 

[rlcwa]

Anyone notice the FBDIMM remark in slide #1? I take it that the chips themselves will be ready for motherboards with FBDIMM slots - any timeline on when those motherboards will appear?

~R

 

[(cf)Eclipse]

Anyone notice the FBDIMM remark in slide #1? I take it that the chips themselves will be ready for motherboards with FBDIMM slots - any timeline on when those motherboards will appear?

~R

shouldn't be too long, seing as newegg was selling fb-dimm ddr2 for a while..