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AMD Next Generation Processor Technology Slides
- Thread starter FrgMstr
- Start date
visaris said:
Indeed.And look what his source is : wikipedia.
You know , posting a wiki link as a tangential proof (where does it say complex MPUs there ? ) in support of your argument looks you're either disingenious or a fool.Take your pick.Let's see some real stuff :
http://www.fabtech.org/index.php?option=content&task=view&id=1390&Itemid=2
Allow me to quote this :
And this is on the good old 90nm process.
Every time I say something I have evidence to back it up.You OTOH use wiki and dubby as a source.Which says everything about your level of knowledge
Lolento said:
They managed to get 150% more wafer starts by using FAB36's building as temporary storage for some equipment from FAB30.
Once FAB36 is completed the equipment is moved back , so production in FAB 30 will shrink.It will be more than compensated though from FAB36.There was a story on the Inq about this "wonder" but I fail to find it right now.
*Arghh...found it.AMD used 2 techniques invented witth the help of the world leading APM :
-MoTSTOF-NOW or Move That Sh*t To the Other Fab NOW!.
and
-MoTSBTWICF-SOMETIME or Move That Sh*t Back To Where It Came From Sometime
http://www.theinquirer.net/default.aspx?article=31095
duby229 said:
Yea, I agree with you, you win
Seems the SEC report from AMD is totally bogus....LMAO
Just my suggestion, instead of reading what AMD does all the time, read about other companies like Motorola, Freescale, Intel, TSMC... They have other philosophies for manufacturing like TPM, TQM, etc... You will learn alot. Open your eyes a little.
150% of capacity is not possible without cutting into cycle times of the actual process which is likely to effect the quality of the end product (Process Engineers at AMD can identify cycle times that are insensitive to quality but at most they will probably gain 10-15% in cycle time, not 50%). APM is not going to change that. I have no doubt that AMD is very efficient with their manufacturing. But efficiency is not magic, it cannot change water to wine.
If in fact that AMD has equipment from another fab to account for the over capacity that then this may be true. However, it only shows that AMD has expansion issues. No manufacturing management will sustain an over-capacity plant for long periods of time. It is a recipe for disaster.
Just my take. And I apologize for being confrontational.
savantu said:"A wise man learns from things he doesn't know while a fool laughs at them."
If you mean I should watch carefully and learn the art of showing my ass and acting like one in a public tech forum, while showing complete disreguard for logical conversation all the while demonstrating stupidity to the highest power then I do not accept.
Perverting and distorting any link to information that comes from industry insiders, analysts, and the very manufacturers themselves simply to dismiss it with savvy comebacks, wit and personality that is not worthy of the rest of us simple minded tech fans eyes.
No sir, when I read what is obviously a strained minds childish and unintellible ramblings I feel my Iq lowering and can only reply with bahahahaha.
But you are right I should learn to cower in fear and hide from what I have determined to be some of the worst fourm trolling and argument fishing that I have ever seen demonstrated on these fine forums.
eblislyge said:
Eloquence is the poor man's argument when he has no argument.
Instead of beind a smart*ss why not refute my claims ? Why don't you show some solid evidence in support of you claims ? Your word only isn't worth the bytes needed to write it...
Show that
-AMD's yields are 80-90% instead of 50%
-Intel uses more than 3-4 FABs for MPUs
-That the product mix for AMD is much higher in favour of DC
-That AMD has better transistor characteristics than Intel
-Better transistor density
-Anything else that I may have missed
Wait , you can't! Your less-than-eloquent response was bahahahahah. I love a good laugh. .Who's the troll Chuckie ?
Majeztik12
Limp Gawd
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how many cores does Vista support?
kemist1117
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savantu, you didnt read the blurb you posted:
"said that yields were at 50 percent at Chartered's Fab7 but sometimes even better than those achieved within AMD's own fab!"
They said that yields overall were at 50 percent but SOMETIMES were even better than those achieved by AMD. The only thing this tells us is that chartered has sustained 50% yields but occasionally spits out something worth a damn.
"said that yields were at 50 percent at Chartered's Fab7 but sometimes even better than those achieved within AMD's own fab!"
They said that yields overall were at 50 percent but SOMETIMES were even better than those achieved by AMD. The only thing this tells us is that chartered has sustained 50% yields but occasionally spits out something worth a damn.
It is now confirmed that the K8L will not ship until Q1 2008, or 18-20 months from now.
They are also reporting that AMD is having trouble with their 65nm process.
K8L will now be competing with Ridgefield, the high-performance successor to the Kentsfield, since Kentsfield will be phased out by the time K8L ships.
They are also reporting that AMD is having trouble with their 65nm process.
K8L will now be competing with Ridgefield, the high-performance successor to the Kentsfield, since Kentsfield will be phased out by the time K8L ships.
BigMacAttack
[H]ard|Gawd
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Pls remember to take what you read from the Inq with a grain of salt. This "proves" nothing, really. We'll have a better idea of when K8L will ship in 3-6 months. Until there is corroborating evidence this is nothing more than mere speculation. It would be wise for everyone to continue to monitor the situation without jumping to conclusions.
|CR|Constantine
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After that article I am more confused now than ever.
So the Inq came up with the name K8L, but only because they heard it from Intel. Where as AMD asked the Inq where they got the name from to which they responded Intel.
But if K8L is the codename for a new processor that will be quad core and be released 1Q 2008 than what pray tell is the processor and more importantly the name of the processor that they taped out a few weeks ago...
(Austin Powers voice) Oh no I have gone cross eyed.
So the Inq came up with the name K8L, but only because they heard it from Intel. Where as AMD asked the Inq where they got the name from to which they responded Intel.
But if K8L is the codename for a new processor that will be quad core and be released 1Q 2008 than what pray tell is the processor and more importantly the name of the processor that they taped out a few weeks ago...
(Austin Powers voice) Oh no I have gone cross eyed.
kemist1117 said:
Both orbit around 50% , sometimes Chartred manages 54-57% and AMD 52% , but as a rule of thumb Chartred goes into high 40s-low 50s while AMD manages low 50s-mid 50s.It's not like this week Chartred manages 20% and next week they hit 90%.
80-90% on complex devices like MPUs is impossible and as feature size goes down the problems related to reliability grow several orders of magnitude.
IBM with Cell which has a die size slightly larger than an X2 manages 10-20% yeilds .Intel got around 30% with 180nm P4.
savantu said:
I gotta call BS...
Anything less then 80% yeild is unmaintainable. If a company is consistantly getting less then 80% yeild, then it is time to evalute the situation....
Right now on AMD's 90nm SOI process the FAB is pushing out about 30M wafers a month... It was designed for 20M.... That means that AMD is at 150% capacity with damn near 100% yeilds....
Savantu of all people you should know anything less then 80% yeilds loses money.
brentpresley
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duby229 said:
Once AGAIN you are full of it. You have ABSOLUTELY NO CLUE WHAT YOU ARE TALKING ABOUT!
If the ASP (Average Selling Price) of the chips is high enough, then it is perfectly economically feasible for a company to produce chips at 50-60% yield and still make good money on them. Heck, even 10-20% is doable IF the price is high enough (Cell, Itanium, and the original Alpha come to mind).
Yield is inversely proportional to die size. If you are getting 80% yield on single core processors, and you double the die size (approximately) to go to dual cores, your yields become (0.80)^2 = 64%.
It is ONLY when companies must cut prices (like right now, when AMD and Intel are in a price war) that ASPs drop like a rock and it is less feasible to make money on the chips.
But we are no where NEAR that point. Neither AMD or Intel disclose their yields OR costs on a per die basis. People with a LOT more insight than you have estimated the cost for single cores at about $35-40 each. Under the current pricing scheme, both companies are still making money, but because of ECONOMIES OF SCALE, Intel is making more.
And QUIT QUOTING THAT DAMN 100% YIELD BS UNLESS YOU CAN BACK IT UP W/ SOME HARD EVIDENCE. And I DON'T want to see some F-ing Inquirer link.
(here is a hint - is it THEORETICALLY impossible to get 100% yields - how do you fit a set of square pegs through a round hole? YOU DON'T! EVEN IF every chip that is etched were perfect, there is ALWAYS wasted silicon on the edges of the (ROUND) wafer that is not big enough to fit a die on. There is ALWAYS wasted silicon. ALWAYS.)
NOW STFU AND GO BACK TO MIDDLE SCHOOL!
duby229 said:
You are 100% correct Dubby. Mature yields are considered to be above at least 80%. You can tell savantu is just making up numbers, not only because they are so far off for both AMD and Intel, but because he is trying to claim specifics: "Both orbit around 50% , sometimes Chartred manages 54-57% and AMD 52%", when it is a known fact that these companies never release specific yield numbers.
The closest thing to a yield number I have heard from an AMD rep was when Hector was questioned about 65nm yields. All he said was that AMD would wait for "mature yields" before aggressively shipping and transitioning to 65nm. When asked what "mature yields" meant, Hector said something about 90% being the minimum but refused to talk about it further. Hector was implying that AMD would wait for "mature yields" before shipping 65nm chips and further claimed that "our competitor" is willing to ship 65nm chips even with poor yields. I don't know if this article is true or not, but it matches wikipedia's idea of mature yields, and agrees with Hans from chip-architect. I wish I could find this article/interview. I think it was out at the beginning of this year, but I don't remember.
He said "near 100%", as in "above 90%". No one is claiming perfect 100% yields. That is practically impossible. Quit twisting his words around.brentpresley said:
Lol, shows what you know about yield calculations. Chips that do not fit entirely on the wafer are not usually counted in yield calculations. While one will get more chips out of a 300mm vs a 200mm wafer, their yields don't magically jump with the transition, because the partially etched dies are not considered. You don't understand the field, so back off dubby; he obviously does.brentpresley said:
brentpresley said:
OK !!!!!!.. We can do this if you really want to.. But the simple fact is we already did... I posted several sources, and AGAIN. I wont do your research for you...
Now you can stop being a !!!!!!, and look at the evidence...
The simple matter of FACT is that AMD is selling pretty damn close to what they are capable of making
Stop being a f'n !!!!!!.
Remember a thing called bins!!
brentpresley
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There is a HUGE difference b/w selling everything they are making, and making everything that is possible out of a wafer. You are claiming the later, and that is PURE BS.
And FYI, NONE of the links you posted prove a thing about your yield claims. NOT A SINGLE ONE gives any specific numbers. They are essentially editorials and provide ZERO HARD EVIDENCE of yields.
And FYI, NONE of the links you posted prove a thing about your yield claims. NOT A SINGLE ONE gives any specific numbers. They are essentially editorials and provide ZERO HARD EVIDENCE of yields.
brentpresley
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visaris said:
LOL - shows how MUCH you know. FYI, dies are NEVER partially etched (i.e. if there is no space at the edge to fit an extra die, it isn't etched). Why? Think of it this way, you have a VERY high frequency UV beam that does the etching. If it goes OFF the wafer while trying to print your CPU, it does damage to the underlying wafer tray and robotics. These are not low radiation machines. You NEVER over etch a wafer.
Now, who OBVIOUSLY doesn't understand the field? Thought so. You don't.
brentpresley said:
OK, I think I'll just show you....
http://www.amd-images.de/PICS/process/550/Image_0084f.jpg
brentpresley
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duby229 said:
ONCE AGAIN. NO PROOF. YOUR YIELD CLAIM IS COMPLETELY BS AND YOU HAVE NOTHING TO BACK IT UP.
I noticed you had not a SINGLE retort to my argument about yields and average selling price. Why? Because I am 100% right.
Pissed you got called out on your BS huh? Well most of us here are capable of seeing right through your idiotic claims. And a few of us
are going to call you out on EVERY SINGLE ONE.You are even FURTHER clueless if you think AMD is the only company that has something like APM. Intel, TI, and IBM have been using automated systems for process adjustment for almost a decade now.
In fact, I would BET AMD learned most of the tricks from IBM (guess who developed SOI for AMD? Yep, IBM).
brentpresley
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duby229 said:
WTF is that supposed to show us?
You can't see anything off a pic that small.
brentpresley said:ONCE AGAIN. NO PROOF. YOUR YIELD CLAIM IS COMPLETELY BS AND YOU HAVE NOTHING TO BACK IT UP.
I noticed you had not a SINGLE retort to my argument about yields and average selling price. Why? Because I am 100% right.
Pissed you got called out on your BS huh? Well most of us here are capable of seeing right through your idiotic claims. And a few of us
You are even FURTHER clueless if you think AMD is the only company that has something like APM. Intel, TI, and IBM have been using automated systems for process adjustment for almost a decade now.
In fact, I would BET AMD learned most of the tricks from IBM (guess who developed SOI for AMD? Yep, IBM).
Dude your clueless... You BET? you dont know? Ah that is right your just a 15 year old kid sittin behind his dad's computer....
(cf)Eclipse
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now would be the time give up, it appears that everyone is against what you're saying.....brentpresley said:
about the yields... time to totally make up some random, but logical numbers now
so let's say that you make a lot of single core, 512kb cached K8's.
15% have a defect in the core itself
15% have a defect in the L2 cache.. since with 512kb K8, the L2 is roughly the same size as the core
5% can't get high enough speed
the rest are able to function at 1.6ghz or higher, amd's lowest bin for the sempron line. so does this mean we have 65% yeilds? no. amd will take the 15% with cache defects, disable 1/2 the cache, and sell them as semprons. now we're technically up to 80% yeild.
if these were dual cores, take the 15% that have a core defect and disable one core to make it a single core. now we're up to 95% yield
obviously, it isn't this simple, and there's a lot more that can go wrong, but disabling the defective part of the die is a very powerful tool to get effective yields up.. to the point where 90% yield is actually quite reasonable. feel free to discredit me cause i pulled numbers out of my ass, but you know i have a damn good point
brentpresley
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(cf)Eclipse said:now would be the time give up, it appears that everyone is against what you're saying.....
about the yields... time to totally make up some random, but logical numbers now
so let's say that you make a lot of single core, 512kb cached K8's.
15% have a defect in the core itself
15% have a defect in the L2 cache.. since with 512kb K8, the L2 is roughly the same size as the core
5% can't get high enough speed
the rest are able to function at 1.6ghz or higher, amd's lowest bin for the sempron line. so does this mean we have 65% yeilds? no. amd will take the 15% with cache defects, disable 1/2 the cache, and sell them as semprons. now we're technically up to 80% yeild.
if these were dual cores, take the 15% that have a core defect and disable one core to make it a single core. now we're up to 95% yield
obviously, it isn't this simple, and there's a lot more that can go wrong, but disabling the defective part of the die is a very powerful tool to get effective yields up.. to the point where 90% yield is actually quite reasonable. feel free to discredit me cause i pulled numbers out of my ass, but you know i have a damn good point
MADE up numbers mean zilch. I can come up w/ 5 different "logical" assumptions. Doesn't mean they are right.
I have still NOT SEEN one shred of evidence for any yield claims.
All duby can do is throw insults instead of hard facts. (shows who's really the 15yo here).
(cf)Eclipse
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but i do have to wonder... you're arguing against him, also without any hard facts. why must you expect facts from him if you won't use them too? seems a touch skewed to me. best we can do when it comes to yields is either:brentpresley said:
1. guess
2. work for amd and be under nda.
brentpresley said:
Dude there are no hard facts....
Get used to it. Yeilds are closely guarded secrets.. Always have been, prolly always will be.
It's called logic, and imperical evidence. AGAIN... I've already shown you what AMD is capable of making, and what they are selling....
They say if you cant stand the heat, get out of the kitchen...
brentpresley said:
Sound familiar? Sounds like a double standard to me.... At least I gave you the benefit of 15, and I bet my guess is closer then yours...
duby229 said:
You have no idea of what you're sourcing as your proof....this is so idiotic that I have to reply on this.
The picture here shows a typical wafer after fab. There is an edge of 3mm-5mm around the perimeter which is typical of the keep out zone at the edge.
Just able to print die on the wafer doesn't mean you get 100%....hahahaha, LMAO
Yield-offs are determined at wafer final test. For new flip chip IC package technology, this is not determine at the stage where the picture showed.
Wafer final test is done after either the flip chip RDL process or the flip chip bumping process which you will not be able to see the die layout as you see in that picture....hahaha
Typical yield-offs cannot be catched visually. Most yield offs are due to unconformity of the wafer surface itself and cannot be corrected.
FYI, just from my experience, new process yields are generally around 40%. With continuous improvement, it can go up to 70% in about 6 - 9 months. Further improvements in process yields will generally take much longer time due to the complexity in the level of DOE (design of experiements) that is involved in further improvements.
I can quote sources of these statements but they are mostly from years of school work and experience.
90%+ yields are possible on large feature size process (0.35um, 0.18um) using newer equipment. In 90nm process, I have never seen anything about 70%, even with large number of binnings.
(cf)Eclipse
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to the rest, i say "ORLY?". i know duby knows that, andi feel that in your haste to critize him, you forgot what exactly he was trying to sayLolento said:
but i wanted to question this statement. where was the line drawn to establish the 40% yield? only 40% of the chips came off the die working as were manufactured?
so then disable cache on the ones that you can to boost yields.
if dual core, disable a core to boost yields more.
next thing that was interesting.. so it can get up to 70% in 6-9 months. no way does it just STOP at 70%, so why the last statement proclaiming that "In 90nm process, I have never seen anything about 70%, even with large number of binnings."
90nm has been around for almost 2 years now. are you telling me that you somehow got ahold of yield info that is very tightly gaurded and can say that it never goes over 70%, thus contradicting your previous statement that it hits 70% in just 6-9 months.
give me a break
brentpresley said:ONCE AGAIN. NO PROOF. YOUR YIELD CLAIM IS COMPLETELY BS AND YOU HAVE NOTHING TO BACK IT UP.
I noticed you had not a SINGLE retort to my argument about yields and average selling price. Why? Because I am 100% right.
Pissed you got called out on your BS huh? Well most of us here are capable of seeing right through your idiotic claims. And a few of us
You are even FURTHER clueless if you think AMD is the only company that has something like APM. Intel, TI, and IBM have been using automated systems for process adjustment for almost a decade now.
In fact, I would BET AMD learned most of the tricks from IBM (guess who developed SOI for AMD? Yep, IBM).
Thank you for getting emotional about silicone. I'm sure behavioral researchers will have a good time with this.
(cf)Eclipse
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hahaha, that's one important thing about online debating. gotta get your point across while still sounding happyObi_Kwiet said:
Lolento said:
Like I said I'm not going to argue with you.... I'll let you think you got the last word in...
If you have specific yeild information then please share it...
My point in posting a link to that wafer was only to show that partial dies are printed, despite what someone else said. Those partail dies are not counted in yeild calculations precisely becouse they are not full dies.
Let me make myself perfectly clear... If you count as many full dies on a wafer., and all the wafers that AMD is capable of producing,,, That is pretty damn close to what AMD is actually selling. Therefore Yeild can be infered.. I dont know what yeild actually is... I'm just taking a guess.
You might want to look into how AMD bins there chips.
(cf)Eclipse said:to the rest, i say "ORLY?". i know duby knows that, andi feel that in your haste to critize him, you forgot what exactly he was trying to say
but i wanted to question this statement. where was the line drawn to establish the 40% yield? only 40% of the chips came off the die working as were manufactured?
so then disable cache on the ones that you can to boost yields.
if dual core, disable a core to boost yields more.
next thing that was interesting.. so it can get up to 70% in 6-9 months. no way does it just STOP at 70%, so why the last statement proclaiming that "In 90nm process, I have never seen anything about 70%, even with large number of binnings."
90nm has been around for almost 2 years now. are you telling me that you somehow got ahold of yield info that is very tightly gaurded and can say that it never goes over 70%, thus contradicting your previous statement that it hits 70% in just 6-9 months.
give me a break
90nm process was hovering at 70% at the time I left my previous work last year in September.
Continuous process improvement never stops. However, it is from my experience that once about 70% yield is reached, further improvement is difficult. But the work for improvement continues.
When cache and cores are disable to improve yield. That technique is called binning in wafer test. I'm saying even with large number of binning, the yield is still difficult to reach 70%.
I don't know exactly what the yield levels are for AMD, Intel, TSMC, SMIC, UMC, or IBM. But I can tell you that the engineers at these companies move around quite often. What I know from one company basically translate to the others.
duby229 said:
I don't need you to give me the last word.
I didn't come to this forum to post or to target you. I come here to read up on hardware recommendations, mobo recommendations, interesting things about case mods...etc
It is very insulting to me (and I'm sure others who are working in this field) when I see people mis-quote information from the web and then try to pass off BS as facts. This is the only reason I'm posting on this thread.
I have used AMD chips from K6-2 to now Athlon64 X2. I am extremely happy with my choice of AMD chips for the past 10 years because I know I was able to pick a chip for its merit regardless of brand (price/performance). I think people should be able pick products based on price/performance instead of brand.
What I think is useless is speculating about performance of future products (this is the reason why everyone hates a paper launch from ATi or Nvidia). What is more useless is arguing about AMD yields or their manufacturing management system to which no one knows anything about unless he/she works at AMD. What is the most useless is people who quote these useless information for the sake of winning a debate.
I think it is really sad that people like you are dumbing down this forum. It is even more sad that you're on the AMD side. People like you were on the Intel side 10 years ago.
So if you continue to post BS as facts, I will continue to call you out. I do not want people who come here to read up on hardware informations to be misinformed.
For your information, you're right about the partial dice not being counted on the yield. However, even full dice along the perimeter has a high defect rate, and they are counted in the yield. I don't think AMD can improve the yield of these full edge dice due to the fact that it is not the process that is causing the defect; the coplanarity of the wafer at the edge is causing most of these defects.
Lolento said:
What's even more useless is those people that argue about other people and there attempts to shed light on the current situation. Then try to pass it off as some sort of holy plight against evil...
Get off my nuts dude. It's fun to swing but there comes a point when the ride is over, and it's time to get off.